This invention relates to semiconductor fabrication processes, and more particularly to antireflective coatings and wiring line processes.
Integrated circuits (ICs) commonly are fabricated on a semiconductor wafer. The wafer typically is cut to form multiple semiconductor substrates or "IC chips". Semiconductor devices are formed on the wafer. Although the label semiconductor is used, the devices are fabricated from various materials, including electrical conductors (e.g., aluminum, tungsten), electrical semiconductors (e.g., silicon) and electrical non-conductors (e.g., silicon dioxide). The semiconductive silicon wafer is subjected to deposition, etching, planarizing and lithographic processes to achieve the many semiconductor devices. Aluminum and aluminum alloy metallization techniques are used to create contacts and interconnects among devices.
The advantages of manufacturing ICs with smaller individual circuit elements so that device density is increased are well known: electronic equipment becomes less bulky, reliability is improved by reducing the number of connections, assembly and packaging costs are minimized, and circuit speeds increase. Interconnect technology is increasingly a limitation in increasing circuit density for very large scale integration (VLSI) devices. In particular, achieving smaller line widths and smaller line spacings typically controls the number of devices that can occur on a semiconductor substrate. The ability to minimize the line widths and line spacings is limited by the lithographic processes, among others.
The term "lithographic process" refers to a process in which a pattern is delineated in a layer of material sensitive to photons, electrons or ions. The principle is similar to that of a photocamera in which an object is imaged on a photo-sensitive emulsion film. While with a photo-camera the "final product" is the printed image, the image in the semiconductor process context typically is an intermediate pattern which defines regions where material is deposited or removed. An anti-reflective material is desired during photolithographic processes to define areas to remain intact (e.g., positive exposure) or to be removed (e.g., negative exposure).
A current problem in patterning small dimensions for very large scale integrated ("VLSI") circuits is notching of line edges, or, more generally, non-uniform line formation. Notching refers to grooves or other uneven cuts (i.e., "notches") detracting from straight edges. Such notching has been less significant when patterning larger line widths and line spacing because the size of the notch relative to the line width or spacing was relatively small. At the smaller dimensions, however, notches can sever or significantly decrease a line width. A severed wiring line, for example, is an open circuit, and thus is defective. Reflection of light off metal lines during photolithography is one cause of notching.
FIGS. 1A and 1B show a notched wiring lines 10, 13, and 15 formed on a semiconductor substrate 11, wherein said lines 10, 13, and 15 are separated by an insulative material 17 disposed over the substrate 11. The wiring line 10 has a portion 12 along its length which is substantially thinner than other portions 14, 16. This thinner portion 12 is more susceptible to electromigration and stress migration. Electromigration is the transport of metal atoms by momentum exchange between electrons and metal ions. As the electrons move under the influence of a field, collisions between the electrons and ions transfer momentum to the ions. The ions in turn move in the direction of electron flow, leaving a vacancy in the wiring line metal. Over time, the vacancies accumulate, forming voids of non-conductivity in the metal. In effect, a defective open circuit occurs.
Stress migration is the atomic migration induced by thermal cycling of a wiring line between high operating temperatures and low environmental temperatures. The thermal cycling causes mechanical stresses on the thin lines, commonly referred to as creeping. The stress increases as the line width decreases. The predominant failure again is voiding in the metal, resulting in defective open circuits in wiring lines. Accordingly, uniform lines are desired to avoid notching and the resulting susceptibility to electromigration and stress migration. Such uniform lines are desired for increasingly smaller line widths and line spacings.
Another cause of migration failures in wiring lines is shrinkage during heat treatment processes. A conventional wiring line includes a conductor layer (e.g., aluminum) and an underlayer (e.g., titanium). During the fabrication processes which produce the wiring line and adjacent integrated circuitry, the titanium and aluminum undergoes a heat treatment process. During such process, adjacent regions of aluminum and titanium react to form a titanium aluminum compound between the titanium layer and the aluminum layer. In one application, the stable compound formed is TiAl.sub.3. In forming the compound, however, the aluminum layer shrinks, resulting in a 4-8% volume loss at the aluminum layer. This volume loss has the undesired effect of increasing stress in the aluminum layer, (e.g., stress increases by 3-4 times for small line dimensions). As a result, voids are prone to form over time due to stress migration and electromigration. At small line dimensions, the metal may even go beyond its yield strength and break, leaving undesired voids after the heat treatment process. Accordingly, there is a need for a wiring line formation process which avoids undue stress upon the conductive layer.
There also is a need for an antireflective coating applied to a semiconductor substrate of a flat panel display device. In a cold cathode field emission display ("FED") device, the quality and sharpness of an illuminated pixel site of the display screen is dependent on the precise control of the electron emission from emitter sites that illuminate a particular pixel site. In forming a visual image, such as a number or letter, different groups of emitter sites must be cycled on or off to illuminate the appropriate pixel sites on the display screen. To form a desired image, electron emission may be initiated in the emitter sites for certain pixel sites while the adjacent pixel sites are held in an off condition. For a sharp image, it is important that those pixel sites that are required to be isolated remain in an off condition.
One factor that may cause an emitter site to emit electrons unexpectedly is the response of semiconductor junctions in the FED drive circuitry to photons. The adverse photons are generated by the luminescent display screen and/or by photons present in the environment (e.g., lights, sunshine). This may affect the junctions by changing their electrical characteristics. In some, cases this may cause an unwanted current to pass across the junction. The unwanted current may initiate electron emission from emitter sites of adjacent pixels. Such emission in turn may cause the adjacent pixel to illuminate when a dark pixel is desired. From a viewer's perspective, illumination of undesired pixels may cause degraded or blurry images. Besides isolation and activation problems, light from the environment and display screen striking junctions on the substrate may cause other problems in addressing and regulating current flow to the emitter sites of the FED cell. Accordingly, there is a need to prevent given junctions from undesired exposure to photons.